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| MX23L3222 32M-BIT MASK ROM (16/32 BIT OUTPUT) FEATURES * Bit organization - 2M x 16 (word mode) - 1M x 32 (double word mode) * Fast access time - Random access: 100ns (max.) - Page access: 30ns (max.) * Page - 8 double words per page * Current - Operating:60mA - Standby:50uA * Supply voltage - 3.3V10% * Package - 70 pin SSOP (500mil) PIN CONFIGURATION A0 A1 A2 A3 A4 A5 VCC D0 D16 D1 D17 VSS VCC D2 D18 D3 D19 D4 D20 D5 D21 VSS VCC D6 D22 D7 D23 VSS A6 A7 A8 A9 A10 A11 A12 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 NC NC NC WORD OE CE VSS D31/A-1 D15 D30 D14 VSS VCC D29 D13 D28 D12 D27 D11 D26 D10 VSS VCC D25 D9 D24 D8 VCC A19 A18 A17 A16 A15 A14 A13 PIN DESCRIPTION Symbol A0~A19 D0~D30 D31/A-1 CE OE WORD VCC VSS NC Pin Function Address Inputs Data Outputs D15 (Word Mode)/ LSB Address (Byte Mode) Chip Enable Input Output Enable Input Double Word/ Word Mode Selection Power Supply Pin Ground Pin No Connection MX23L3222 ORDER INFORMATION Part No. Access Page Access Time MX23L3222MC-10 100ns MX23L3222MC-12 120ns Time 30ns 45ns 70 pin SSOP 70 pin SSOP Package P/N:PM0396 REV. 2.0, OCT. 19, 2001 1 MX23L3222 MODE SELECTION CE H L L L OE X H L L WORD X X H L D31/A-1 X X Output Input D0~D15 High Z High Z D0~D15 D0~D15 D16~D31 High Z High Z D16~D31 High Z Mode Double Word Word Power Stand-by Active Active Active BLOCK DIAGRAM A0/(A-1) A2 A3 A19 CE BYTE OE Address Buffer Memory Array Page Buffer Page Decoder Word/ Byte Output Buffer D0 D31/(D15) P/N:PM0396 REV. 2.0, OCT. 19, 2001 2 MX23L3222 ABSOLUTE MAXIMUM RATINGS Item Voltage on any Pin Relative to VSS Ambient Operating Temperature Storage Temperature Symbol VIN Topr Tstg Ratings -1.3V to VCC+2.0V (Note) 0 to 70 C C -65 to 125 C C Note: Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -1.3V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns. DC CHARACTERISTICS (Ta = 0C ~ 70 VCC = 3.3V10%) C, Item Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (TTL) Standby Current (CMOS) Input Capacitance Output Capacitance Symbol VOH VOL VIH VIL ILI ILO ICC1 ISTB1 ISTB2 CIN COUT MIN. 2.4V 2.2V -0.3V MAX. 0.4V VCC+0.3V 0.8V 5uA 5uA 60mA 1mA 50uA 10pF 10pF Conditions IOH = -0.4mA IOL = 1.6mA 0V, VCC 0V, VCC tRC = 100ns, all output open CE = VIH CE>VCC-0.2V Ta = 25C, f = 1MHZ Ta = 25C, f = 1MHZ AC CHARACTERISTICS (Ta = 0C ~ 70C, VCC = 3.3V10%) Item Read Cycle Time Address Access Time Chip Enable Access Time Page Mode Access Time Output Enable Time Output Hold After Address Output High Z Delay Symbol tRC tAA tACE tPA tOE tOH tHZ 23L3222-10 MIN. MAX. 100ns 100ns 30ns 30ns 30ns 0ns 20ns 23L3222-12 MIN. MAX. 120ns 120ns 45ns 45ns 45ns 0ns 20ns Note: Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested. P/N:PM0396 REV. 2.0, OCT. 19, 2001 3 MX23L3222 AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Level Output Timing Level Output Load 0.4V~ 2.4V 10ns 1.5V 0.8V and 2.0V See Figure IOH (load)=-04.mA DOUT IOL (load)=1.6mA C<100pF Note:No output loading is present in tester load board. Active loading is used and under software programming control. Output loading capacitance includes load board's and all stray capacitance. TIMING DIAGRAM RANDOM READ ADD ADD tACE ADD tRC ADD CE tOE OE tAA tOH tHZ DATA VALID VALID VALID PAGE READ A3-A19 VALID ADD (A-1),A0,A1,A2 1'st ADD tAA 2'nd ADD tPA VALID VALID 3'rd ADD DATA VALID Note: CE, OE are enable. Page size is 8 double words in 32-bit mode, 16 words in 16-bit mode. P/N:PM0396 REV. 2.0, OCT. 19, 2001 4 MX23L3222 REVISION HISTORY Revision 1.8 Description AC Characteristics: The page mode access time (tPA) and output enable time (tOE) are changed as 45ns instead of 50ns. Added 100ns speed grade. Package: Added 100 pin TQFP package, dimension is 14mm x 14mm x 1mm. AC CHARACTERISTICS tOH 10ns-->0ns Delete package:100-pin TQFP Page Date MAR/25/1998 1.9 2.0 P3 P1,2 JAN/29/1999 OCT/19/2001 P/N:PM0396 REV. 2.0, OCT. 19, 2001 5 MX23L3222 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-6688 FAX:+886-3-563-2888 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 6 |
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